In this role, you will be participating verification plan, verification strategy and verification environment architecture discussions, as well as implementation part of E2E key verification components of key projects
Responsibilities You will be participating part of verification plan based on verification requirements, participating verification strategy and verification environment architecture decisions which can meet verification requirements of a project. You will execute some verification tasks with team members to make sure that the verification goals can be accomplished on time.
Key qualifications you hold include PhD or M.Sc. in Computer/Micro-electronics Engineering or equivalent degree PhD or 2 years + M.Sc. of relevant experience in ASIC verification Experience on verification languages and methodologies: SystemVerilog, VMM/UVM, Coverage-Driven Constraint Random functional verification, assertions, formal verification Experience in understanding, analyzing digital design Scripting skill Preferable: Perl, Python, System-C Mixed signal verification is a plus